Placement

• Placement is a step in the Physical Implementation process of placing the standard cell in a standard cell rows in order meet the timing, congestion, and utilization.
• An input to the placement is floorplan database or def.
• For the placement, complete standard cell area will be divided into pieces known as bins or also known as bucket. The size of bin may vary from design to design.
• There are two steps in placement:

1. Global placement
2. Detail placement

Global Placement: As a part of global placement all the standard cells will place in standard cell rows but there may be some overlap of standard cells.

Detail Placement: All standard cells on standard cell rows will legalized, refined and their will not be any overlaps.

• Once the placement is done, than we have to check timing as well as congestion.
• Outputs from the placement will be netlist, def and spef.

NOTES:

Standard Cell Row Utilization: It is defined as the ratio of the area of the standard Cells to the area of the chip minus the area of the macros and area of blockages.

Area (Standard Cells)

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Area (Chip) - Area (Macro) – Area (Region Blockages)

Congestion: If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

• Timing checks to perform after placement: congestion issues, HFN synthesis, capacitance fixing, Transition fixing, setup fixing.

• Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering and can reorder to optimize it. it maintains the number of flops in a chain.
• During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion. This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains. Because of scan chain reordering patterns generated earlier is of no use.
• In placement stage only different types of special cells are added. They are Spare cells, End cap cells, tie cells, etc.

Standard cells: the designer neither uses predesigned logic cells such as AND gate, NOR gate, etc. These gates are called Standard Cells. The advantage of Standard Cell ASIC’s is that the designers save time, money and reduce the risk by using a predesigned and pre-tested Standard Cell Library

Tie cells : The tie cells are used to connect the floating input to either a VDD or VSS without any change in logic functionality of circuit.

Spare cells : Whenever it is required to perform some functional ECO (Engineering change order) , spare cells would be used .These are extra cells, floating in an ASIC design they are also apart of standard cell library and if you want to include some more functionality, after the base tape out of chip by using spare cells.

End cap cells: End caps are placed at the end of cell rows and handle end-of-row well tie-off requirements End caps are used to connect power and ground rails across an area and are also used to ensure gaps do not occur between well or implant layers which could cause design rule violations.

Pre requisites of CTS include, ensuring that the design is placed and optimizes, ensuring that the clock tree can be routed i.e., taking care of congestion issues, power and ground nets are pre-routed.

The inputs are placement database or design exchange format file after the placement stage and clock tree constraints.