Clock reconvergence pessimism (CRP) is a difference in delay along the common part of the launching and capturing clock paths.
the most common causes of CRP are reconvergent paths in clock network, and different min and max delay of cells in the clock network.
CRP is an undesired effect.
clock reconvergence pessimism is an accuracy limitation of STA in general.
The inaccuracy occurs when the analysis tool compares two different clock paths that partially share a common physical path segment, and it assumes the shared segment has a minimum delay for one path and a maximum delay for the other path.
This condition can occur any time that launch and capture clock paths use different delays of reconvergent logic.
The two clock paths that feed into the multiplexer A cannot be active at the sametime, but an analysis could consider
Below is an example, both the shorter and longer paths for one setup or hold check, even without case analysis.
pt_shell> set_operating_conditions -analysis_type \
on_chip_variation -min MIN -max MAX
pt_shell> set_timing_derate -net -min 0.80 -max 1.00
on_chip_variation -min MIN -max MAX
pt_shell> set_timing_derate -net -min 0.80 -max 1.00
here, command set up a variation analysis using a 20% derating that is performed at 100% worst case and then at 80% worse case and repeated for best case also.
The problem arises when the clock network diverges from the common segment, here in above example clock diverges from the U1, resulting in two path.
Now, using above PT command as mention, we are doing min/max analysis using On chip variation.
In the setup check, the second flip-flop,
In the setup check, the second flip-flop,
path-1: clock path to source path ( CLK to LD1/cp) at the 100% worst case, and
path-2: clock path to destination path ( CLK to LD2/cp) at the 80% worst case
(this is because, while setup analysis data path have max delay and clock path have min delay)
This is valid approach beacuse test is pessimistic
here, path-1 and path-2 share a clock tree until the ouput of U1.
the setup check considers that cell U1 simultaneously has two different delays,
min= 0.64 and max= 0.80
resulting in a pessimistic analysis delays in the amount of 0.16.
min= 0.64 and max= 0.80
resulting in a pessimistic analysis delays in the amount of 0.16.
so, test is more pessimistic by 0.16 value and it must be remove for more realistic.
By default, the CRPR setting is false
To enable CRPR:
pt_shell> set timing_remove_clock_reconvergence_pessimism TRUE
Example timing report showing CRPR
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : my_design
****************************************
Startpoint: LD1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: LD2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.40 1.40
LD1/CP (FD2) 0.00 1.40 r
LD1/Q (FD2) 0.60 2.00 f
U1/z (AN2) 3.20 5.20 f
data arrival time 5.20
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : my_design
****************************************
Startpoint: LD1 (rising edge-triggered flip-flop clocked by CLK)
Endpoint: LD2 (rising edge-triggered flip-flop clocked by CLK)
Path Group: CLK
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock CLK (rise edge) 0.00 0.00
clock network delay (propagated) 1.40 1.40
LD1/CP (FD2) 0.00 1.40 r
LD1/Q (FD2) 0.60 2.00 f
U1/z (AN2) 3.20 5.20 f
data arrival time 5.20
clock CLK (rise edge) 6.00 6.00
clock network delay (propagated) 1.16 7.16
clock reconvergence pessimism 0.16 7.32
clock uncertainty 0.00 7.32
LD2/CP (FD2) 7.32 r
library setup time -0.20 7.12
data required time 7.12
---------------------------------------------------------------
data required time 7.12
data arrival time -5.20
---------------------------------------------------------------
slack (MET) 1.92
clock network delay (propagated) 1.16 7.16
clock reconvergence pessimism 0.16 7.32
clock uncertainty 0.00 7.32
LD2/CP (FD2) 7.32 r
library setup time -0.20 7.12
data required time 7.12
---------------------------------------------------------------
data required time 7.12
data arrival time -5.20
---------------------------------------------------------------
slack (MET) 1.92
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