Noise Margin

Noise margin is a parameter closely related to the input-output voltage characteristics. This parameter allows us to determine the allowable noise voltage on the input of a gate so that the output will not be affected. The specification most commonly used to specify noise margin (or noise immunity) is in terms of two parameters-
The LOW noise margin, NML, and the HIGH noised margin, NMH.
NML is defined as the difference in magnitude between the maximum LOW output voltage of the driving gate and the maximum input LOW voltage recognized by the driven gate. Thus,
NML (NOISE MARGIN low) = Vil - Vol

The value of NMH is difference in magnitude between the minimum HIHG output voltage of the driving gate and the minimum input HIGH voltage recognized by the receiving gate.Thus,
NMH (NOISE MARGIN high) = Voh - Vih

following to two figure hlep you to understand it better,

consider the following output characteristics of a CMOS inverter. Ideally, When input voltage is logic '0', output voltage is supposed to logic '1'. Hence Vil (V input low) is '0'V and Voh (V output high) is 'Vdd'V.
Vil = 0
Voh = Vdd 

Ideally, when input voltage is logic '1', output voltage is supposed to be at logic '0'. Hence, Vih (V input high) is 'Vdd', and Vol (V output low) is '0'V.
Vih = Vdd
Vol = 0 

Noise Margins could be defined as follows :

NML (NOISE MARGIN low) = Vil - Vol = 0 - 0 = 0
NMH (NOISE MARGIN high) = Voh - Vih = Vdd - Vdd = 0 

But due to voltage droop and ground bounce, Vih is usually slightly less than Vdd i.e. Vdd', whereas Vil is slightly higher that Vss i.e. Vss'. 

Hence Noise margins for a practical circuit is defined as follows : 

NML  (NOISE MARGIN low) = Vil - Vol = Vss' - 0 = Vss'

NMH (NOISE MARGIN high) = Voh - Vih = Vdd - Vdd' 

Following figure, explain about input and output characteristics of each transitors