ERC Rules check for things such as:
- Floating gates.
- Wrong transistor connections (Source and Drain connected together for instance).
- Floating interconnect, Metal, Poly
- Shorted Drain & Source of a MOS
- No substrate- or well contact ('figure having no stamped connection')
- Different contacts of substrate / well are connected to different nets
- Distance of MOS to next substrate / well contact too large (Latchup rule)
what is the difference between LVS and ERC??
ReplyDeleteThanks in Advance!!
lvs checks for functionality of netlist or design. where erc is the reliability checks which cannot be checked in lvs
ReplyDeletedon't this ERC check not covered in DRC check please specify the difference between DRC and ERC checks
ReplyDeleteNo DRC will check for min spacing /min width/max width or base violations. Opens and shorts are also covered in LVS but LVS will compare netlist and layout. If there is a short in netlist and layout both LVS will not catch it. ERC prevents that from happening as it check the reliability of design.
DeleteWhat is the difference between ERC and PERC
ReplyDeleteerc is electrical rule check which will check the devices functionality wrt physically like psub is connected to vdd and nwell is connected to vdd or not, where as in perc all the device connections will be validated logically not physically
Deleteboth are same
ReplyDeleteWhat is the difference between vectored and vectorless in RV simulations?
ReplyDelete