Layout vs Schematic Verification (LVS)

• Verify that physical implementation is consistent with the above gate and RTL level design representations

• Errors may have occurred due to 

–Errors in physical design tools

–Manual changes in layout

• Verification is primarily graphical or ``topological’’:   gate identification from transistor networks, subgraph isomorphism

Goals: Functionality

Analysis Inputs:

- Foundary or library vendor : Library & Spice Netlist

- Design Data: Mask Data, Logic Netlist

Typical checks perfomed

- connectivity recognition

- device recognition

What LVS does
3 Steps:
1. Extract schematic netlist
2. Extract the layout netlist 
3. Compare the two netlists

In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:

1. Shorts: Two or more wires that should not be connected have been and must be separated.
2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.
3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device)
4. Missing Components: An expected component has been left out of the layout.
5. Parameter Mismatch