VIRTUAL CLOCK

- A virtual clock can be defined as a clock without any source or in other words a virtual clock is a clock that has been defined, but has not been associated with any pin/port.

- It does not physically exist in the design but it does exist in the memory. It is used as a reference to constrain the interface pins by relating the arrivals at input/output ports. 

We can simply define the virtual clock by the create_clock command but we don’t need to give any generation point since for virtual clock there is no actual clock source in the design,

create_clock -name VIR_CLK -period 10 -waveform {0 5}

An example where virtual clock is applicable is shown below-

The design under analysis gets its clock from CLK_IN but the clock driving input port OBJECT_IN is CLK_DRIVER1.How are we supposed to specify the IO constraint on input port OBJECT_IN in such cases? Output port OBJCET_OUT faces the same issue.

To handle such cases, a virtual clock can be defined with no specification of the source port/pin

The virtual clocks for clock CLK_DRIVER1 and CLK_DRIVER2 is defined as follows-

create_clock -name VIR_CLK_DRIVER1 -period 10 -waveform {2 8}create_clock -name VIR_CLK_DRIVER2 -period 8 -waveform {0 4}

Now, the IO constraints can be specified relative to this virtual clock

set_input_delay -clock VIR_CLK_DRIVER1 -max 2.7 / [get_ports OBJ_IN]

set_input_delay -clock VIR_CLK_DRIVER2 -max 4.5 / [get_ports OBJ_OUT]

The figure 2 shows the timing relationships on the input path. This constrains the input path in the design under analysis to be 5.3ns or less. 

Figure 3 shows the timing relationships on the output path. This constrains the output path in the design under analysis to be 3.5ns or lessApplying o/p delay with respect to a real clock causes input ports to get relaxed and output ports to get tightened after clock tree has been built.

TCD (Test-key Critical Dimension) Cell

                     

For technology nodes below 40nm, there are few important rules that must be considered while creating the floorplan.


In fabrication of semiconductors, the minimum line width of the circuit element is called critical dimension (CD). The smaller the circuit element is, the less variation of the CD is allowed. So fabrication of these smaller elements is a big challenge due to critical dimension uniformity (CDU) which impacts the device performance and its characteristics. CDU is a major contributor to yield drop out in deep sub micron technologies Thus, many techniques for improving the critical dimension uniformity are developed,


TCD structures are placed to monitor these various processes variation on the die.

The TCD structure is required to be placed at regular intervals throughout the chip.It could be a significant size, which may need to be allocated on the die early on.
This may impact a floorplan of a block at a later stage if this fact is not considered early on, such as in a block packed with memories.

These are inserted after power planning also we can stack BEOL TCDs over FEOL TCDs to save placement area but BEOL TCDs with metal layer M cannot place over layer M routing.
If a FEOL TCD is on layer M routing, then a BEOL TCD with metal layer M cannot stack with this FEOL TCD.
TCD width and height are not even multiples of unit tile width and height. They are placed
similar to regular macros.


This is one of few of the mandatory components that must be considered in the early stages of full-chip floorplanning, and must be considered for block-level floorplanning.