Scan Chain Reordering

It is the process of reconnecting the scan chains in a design to optimize for routing by reordering the scan connection which improve timing and congestion.
Since logic synthesis arbitrarily connects the scan chain, we need to perform scan reorder after placement so that the scan chain routing will be optimal
Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it & it maintains the number of flops in a chain.

Physical Netlist is reordered based on placement
Reordered scan chain requires much less routing resources in the example design.

Congestion Effect:

During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion.

Timing Effect:

This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains.
Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.