Cells Types in PD

In Physical Design flow, there are various kinds of cells used for several functionality. Each individual cells has there own functionality with which they are implemented in design. Here are some of the list of cells and their basic importance.

Spare Cells

When the design is tape-out and afterwards there is a requirement to fix some bug then it is not possible to fix if we haven’t provided spare cells. These are kind of floating cells which are thrown in design so that after tape-out if some bugs are needed to fix, we can take use of it.There would be inclusion of approximately 5% of spare cells in the whole design, not more than that.

Decap Cells 

They are temporary capacitors which are added in the design between power and ground rails to counter the functional failure due to dynamic IR drop. Dynamic IR Drop happens at the active edge of the clock at which a high current is drawn from the power grid for a small duration. If power source is far from a flop the chances are there that flop can go into metastable state. To overcome decaps are added, when current requirement is high this decaps discharge and provide boost to the power grid.

Detailed Discussion:http://www.cadence.com/Community/forums/p/11345/17149.aspx

Tie Cells

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. These cells are part of standard-cell library. The cells which require Vdd (Typically constant signals tied to 1) connect to Tie high cells The cells which require Vss/Gnd (Typically constant signals tied to 0) connect to Tie Low cells.

For more details:

http://www.cadence.com/Community/forums/p/12129/16444.aspx

Well taps (Tap Cells)

They are traditionally used so that Vdd or GND are connected to substrate or n-well respectively. This is to help tie Vdd and GND which results in lesser drift and prevention from latchup.End cap Cells: The library cells do not have cell connectivity as they are only connected to power and ground rails, thus to ensure that gaps do not occur between well and implant layer and to prevent the DRC violations by satisfying well tie-off requirements for core rows we use end-cap cells.

Filler cells

Filler cells are used to establish the continuity of the N- well and the implant layers on the standard cell rows, some of the small cells also don’t have the bulk connection (substrate connection) because of their small size (thin cells). In those cases, the abutment of cells through inserting filler cells can connect those substrates of small cells to the power/ground nets. i.e. those thin cells can use the bulk connection of the other cells (this is one of the reason why you get stand alone LVS check failed on some cells).