Fixing Hold

There are few ways we can fix hold without effecting setup violations ,

All data verified on 16nm design,

1) Swapping lower vt cells to higher vt is the best way to improve hold.

2) Also we can use delay cells if not able to improve hold through  vt swaping.
We need to go through a procedure if we want to fix hold in automated way.

a) first we need to take setup  slack limit on each and every pin of design and  finding pin with worst setup from all corner.
so now we have pins with worst setup so now we can fix hold by adding delay cells by finding setup margin of pin where we want to add delay cells.

b) Now we can find all timing paths on which hold is violated .

c) For different hold violation limit it will add different delay cells.

Hold slack,

limit 1   : -0.005
limit 2   : -0.015
limit 3  :  -0.035

Buffers can be used as : buf, 16_svt_delay25, 16_svt_delay50, 16_svt_ delay75


Data on setup margin limit for each buffer in different blocks,
 
        Buffer                                        delay after adding buffer          
16_svt_delay25                                  17ps - 89ps          
 Comment : For 4-5 cells its 137ps that because of long nets means high transition  as doing hold fix through script after functional Eco implementation.
16_svt_delay50                                  37ps - 112ps
16_svt_delay75 :                                53ps - 117ps

 hold slack limit                           setup margin                        buffers
 slack >  -0.05                                50ps                                16_lvt_sbuf
-0.005 <=slack>= --0.015               100ps                             16_svt_delay25
-0.015 <=slack>= --0.035               120ps                             16_svt_delay50
 slack < -0.035                              150ps                             16_svt_delay75


d) At last we can go through each path from endpoint to startpoint.and wherever we will find setup margin it will stop searching and  attach delay cell to that pin.

for being more pessimistic we can modify script to search for best margin in particular path and at that pin attach delay cell.

for ex. if we have to add delay25 cells we need margin of 100ps and we found 100ps margin at 1st level from endpoint to startpoint way but if we go little more ahead than we found margin of 150 ps which is best margin so script will attach delay cell to pin with 150ps margin.

Advantage with not searching for best margin that script will attach delay cell at  end  of  the path which can improve hold violations of other startpoints also for which this endpoint is common till that point.
So in the end it wilt help to add less delay cells for design compare to searching for best margin.

Comparison on adding delay cells for best margin and till limit,

 Total 80 paths which need to fix,
Starting from endpoint
With Best margin limit          :    Added 48 delay cells to fix hold completely
Starting from Endpoint
with Threshold limit              :    Added 43 delay cells to fix hold completely
Starting from startpoint
with Threshold limit              :    Added 44 delay cells to fix hold completely

3)If their is very less hold violation in design and we don't want to add delay cells or swap cells than we can reroute  or detour the net which will add some delay in path and fix the hold without effecting setup.