Floorplaning

Build a chip, in many ways same as building an apartment

Apartment

chip

Comparison:

> Both built in layers from ground to up

> Apartment have proper parking for cars, Chips have IO pad

> Apartment have rooms, Chips have macros

> For connectivity, Apartment have stair-case vs Chips have interconnects 

> Bricks, cement, metal rods in the case of apartments, Silicon atoms, dopants and metals in the case of chips

> Builds using a floorplan, 

    - all rooms have own functions in case of apartments

    - all module have own function in case of chips

Floor-planning is a process of arranging structures (macros, complex cell, I/O cells etc) placing close together in such a way to meet the timing (delay) and they occupy less area.

> The main objectives of floor planning are arriving at the optimum shape and size to achieve smallest size to reduce the cost of the total chip for meeting specification

> Nowadays, In deep submicron technology: the signal integrity issues like X-talk, EM, Hot electron becomes more important issues and this influences the die size also.

> For Xtalk issues comes with the metal pitch, EM comes in picture due to metal layers, hot electron due to voltage scaling problem at the lower node and these all issues have affect on die size.

• Inputs for floorplanning: 

  - Gate level Netlist

  - Libraries (.lef &.lib)

  - Constraints 
•  Outputs of floorplan: floorplan of the design in the form of DEF file

• During floorplanning, following steps are to be done:

1. Initialization of a floorplan of appropriate dimension
2. Placement of I/O pins
3. Macro placement considering the communication between them through fly lines.
4. Creation of power straps.
5. Applying appropriate placement blockages near the macros, near the I/O pins, densely packed cell areas etc.
6. Pre-Placement of Tap cells, switch cells, ESD cells, Isolation cells for Low power design-LPD
7. Creation of multiple voltage, power domains for LPD 
8. Clustering of level shifter between the different power domain
9. etc

Notes:

• The final timing, quality of the chip depends on the floorplan design.

Macros (Memories): 

To store information using sequential elements takes up lot of area. A single flip flop could take up 15 to 20 transistors to store one bit. Therefore special memory elements are used which store the data efficiently and also do not occupy much space on the chip comparatively. These memory cells are called macros.

Floor planning control parameters like aspect ratio, core utilization etc are defined as follows:-

• Aspect ratio (AR): It is defines as the ratio of the width to height of the chip. The aspect ratio should take into account the number of routing resources available. If there are more horizontal layers, then the rectangle should be long and width should be small and vice versa if there are more vertical layers in the design
• Concept of Rows: The standard cells in the design are placed in rows. All the rows have equal height and spacing between them. The width of the rows can vary. The standard cells in the rows get the power and ground connection from VDD and VSS rails which are placed on either side of the cell rows. Sometimes, the technology allows the rows to be flipped or abutted, so that they can share the power and ground rails.
• Core: Core is defined as the inner block, which contains the standard cells and macros. There is another outer block which covers the inner block. The I/O pins are placed on the outer block.
• Power Planning: Signals flow into and out off the chip, and for the chip to work, we need to supply power. A power ring is designed around the core. The power ring contains both the VDD and VSS rings. Once the ring is placed, a power mesh is designed such that the power reaches all the cells easily. The power mesh is nothing but horizontal and vertical lines (straps) on the chip. One needs to assign the metal layers through which you want the power to be routed. During power planning, the VDD and VSS rails also have to be defined.
• I/O Placement: There are two types of I/O‘s.

Chip I/O: The chip contains I/O pins. The chip consists of the core, which contains all the standard cells, blocks. The chip I/O placement consists of the placement of I/O pins and also the I/O pads. The placement of these I/O pads depends on the type of packaging.

Block I/O: The core contains several blocks. Each block contains the Block I/O pins which communicate with other blocks, cells in the chip. This placement of pins can be optimized.

• Pin Placement: Pin Placement is an important step in floorplaning. The pin placement can be done based on timing, congestion and utilization of the chip.

Pin Placement in Macros: It uses up M3 layers most of the time, so the macro needs to be placed logically. The logical way is to put the macros near the boundary. If there is no connectivity between the macro pins and the boundary, then move it to another location.

• Concept of Utilization: Utilization is defined as the percentage of the area that has been utilized in the chip. In the initial stages of the floorplan design, if the size of the chip is unknown, then the starting point of the floorplan design is utilization.

There are three different kinds of utilizations.

Chip Level utilization: It is the ratio of the area of standard cells, macros and the pad cells with respect to area of chip.

Area (Standard Cells) + Area (Macros) + Area (Pad Cells)

-------------------------------------------------------

Area (chip)

Floorplan Utilization: It is defined as the ratio of the area of standard

 

cells, macros, and the pad cells to the area of the chip minus the area of the

sub floorplan.

�� Area (Standard Cells) + Area (Macros) + Area (Pad Cells)

----------------------------------------------------------------------------

Area (Chip) – Area (sub floorplan)

Standard Cell Row Utilization: It is defined as the ratio of the area of the standard Cells to the area of the chip minus the area of the macros and area of blockages.

Area (Standard Cells)

----------------------------------------

Area (Chip) - Area (Macro) – Area (Region Blockages)

• Macro Placement: As a part of floorplaning, initial placement of the macros in the core is performed. Depending on how the macros are placed, the tool places the standard cells in the core. If two macros are close together, it is advisable to put placement blockages in that area. This is done to prevent the tool from putting the standard cells in the small spaces between the macros, to avoid congestion.
• Few of the different kinds of placement blockages are:

a. Standard Cell Blockage: The tool does not put any standard cells in the area specified by the standard cell blockage.

b. Non Buffer Blockage: The tool can place only buffers in the area specified by the Non Buffer Blockage.

c. Blockages below power lines: It is advisable to create blockages under power lines, so that they do not cause congestion problems later. After routing, if you see an area in the design with a lot of DRC violations, place small chunks of placement blockages to ease congestion. After Floor planning is complete, check for DRC (Design Rule check) violations. Most of the pre-route violations are not removed by the tool. They have to be fixed manually.

• The factors to be considered during macro placement

1. First check flylines i.e. check net connections from macro to macro and macro to standard cells. If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.
2. If input pin is connected to macro better to place nearer to that pin or pad.
3. If macro has more connection to standard cells spread the macros inside core.
4. Avoid criscross placement of macros.
5. Avoid bottleneck
6. Use soft or hard blockages to guide placement engine.

• I/O cells in the floorplan: the I/O cells are the one which interact in-between the blocks outside of the chip and to the internal blocks of the chip. In floorplan these I/O cells are placed in between the inner ring (core) and the outer ring (chip boundary). These I/O cells are responsible for providing voltage to the cells in the core. These I/O cells are responsible for providing voltage to the cells in the core. For example: the voltage inside the chip for 90nm technology is about 1.2 Volts. The regulator supplies the voltage to the chip (Normally around 5.5V, 3.3V etc).

The next question which comes to mind is that why is the voltage higher than the voltage

Inside the chip?

The regulator is basically placed on the board. It supplies voltage to different other chips

on board. There is lot of resistances and capacitances present on the board. Due to this,

the voltage needs to be higher. If the voltage outside is what actually the chip need inside,

then the standard cells inside of the chip get less voltage than they actually need and the

chip may not run at all. So now the next question is how the chips can communicate between different voltages? The answer lies in the I/O cells. These I/O cells are nothing but Level Shifters. Level Shifters are nothing but which convert the voltage from one level to another The Input I/O cells reduce the voltage coming from the outside to that of the voltage needed inside the chip and output I/O cells increase the voltage which is needed outside of the chip. The I/O cells acts like a buffer as well as a level shifter.

• Add the tap cell/ switch cells : At the floor plan stage we have to add the tap cell, with some spacing in staggred format.The tap cell are cell which are used connect the VDD and VSS to the substrate and well connectivity.By using tap cell we can remove latch up problem

• Core Limited & I/O Limited Designs: In core limited design core is densely packaged and in I/O limited design I/O are densely packed which limits the size of the chip.
• Complex cells: The complex cells are cells which are made of groups of standard cells based on functionality requirement. This cells height is greater than standard cell and less than marcos.