SDC (Synopsys Design Constraints)

The rules that are written are referred to as constraints and  are essential to meet designs goal in terms of Area, Timing and Power to obtain the best possible implementation of a circuit.

There is a common format, for constraining the design, which is supported by almost all the tools, and this format is called SDC - Synopsis Design Constraints format.

The file is saved with an .sdc extention
SDC syntax is a TCL based format, that is, all commands follow the TCL syntax

SDC contains mainly following constraints that are very essential for design

• Clock definition
• Generated clock
• Input/Output delay
• Min/Max delay
• False path
• Multi cycle path
• Case analysis
• Disable timing arcs

The constraints are the following types according the commands types:

• Basic commands
• Object Access Commands
• Timing Commands
• Environment Commands
• Multi-Voltage Commands

Basic Constraints commands

these commands used to set the attributes from that instance

cmd:    set: used to define variables

for example: set_units [-capacitance cap_unit] [-resistance res_units]

                                     [-time time_unit] [-voltage voltage_unit]

                                     [-current current_unit] [-power power_unit]

Object Access Constraints commands

These commands specify how to access objects in a design instance.

these commands are used to get the location of an object in the design.

the object can be a cell, a block, a port, a pin, or anything else in the design.

for example: 

      all_clocks

      # Returns a collection of all clocks.

      Examples:

      foreach_in_collection clkvar [all_clocks] {

       . . .}

      set_clock_transition 0.150 [all_clocks]

      get_libs [-regexp] [-nocase] patterns

      # Returns a collection of libraries that are currently

      # loaded in the design.

for more commands refer this book : Static Timing Analysis for Nanometer Designs A Practical Approach 

Timing Constraints commands

these commands are related to timing specifications of the design

which contains,

• Clock definition          : create_clock
• Generated clock          : create_generated_clock
• Clock transition          : set_clock_transition
• Clock Uncertainty      : set_clock_uncertainty 
• Clock Latency            : set_clock_latency 
• Propagated clock        : set_propagated_clock
• Disable timing            : set_disable_timing
• False path                   : set_false_path                     
• Input/Output delay     : set_input_delay & set_output_delay
• Min/Max delay           : set_min_delay / set_max_delay
• Multicycle path          : set_multicycle_path

Environmental constraints

these commands are used to setup the environment of the design under analysis

commands are:

set_driving_cell
set_input_transition
set_load
set_max_fanout
set_max_area
set_operating_conditions
set_wire_load_model
set_case_analysis.......etc

Multi-Voltage Commands
these commands apply when multi-voltage islands are present in s design.
commands are:
create_voltage_area
set_level_shifter_strategy
set_level_shifter_threshold

set_max_dynamic_power

set_max_leakage_power