Clock

Design includes the following types of Clock information:

• Multiple clocks:

we can define multiple clocks that have different waveforms and frequencies. 

Clocks can have real sources(ports and pins) or can be virtual( no real source) in the design.

• Gated clock

A gated clock is a clock signal 

under the control of the gating logic

• Generated Clocks

A generated clock is a clock signal generated from another clock signal by a circuit within the design itself, such as a clock divider

• Clock Transition times

 the transition time is the amount of time it takes for the signal to change from one logic state to anoher

• Clock network delay and skew:

we specify the delay of the clock network relative to the source called clock latency  and

the variation of the arrival times of the clock at the destination points in the clock network called clock skew

• Clock Latency: it can be ideal or propagated clocks

it has two types 1). Source Latency 2). Network Latency

Source latency is the delay between the ideal waveform to the source pin or port.

Network latency is the delay between the source pin or port to register clock pin 

If we specify the clock as propagated than PT can automatically compute the clock source latency

If not than user specified value is consider for clock source latency

Fig: External Source Latency

Propagated latency calculation is usually inaccurate for prelayout design because the parasitics are unknown.
For prelayout designs, you can estimate the latency of each clock and directly set that estimation with the
set_clock_latency command and it is known as ideal clocking

To specify an external uncertainty for source latency,
use the -early  and -late options of the set_clock_latency command.

For example, consider a source latency that can vary from 1.5 to 2.5ns as shown in above fig.
to specify this type of source latency, you can use commands such as following:

pt_shell> set_clock_latency 1.5 -source -early [get_clocks CLK]
pt_shell> set_clock_latency 2.5 -source -early [get_clocks CLK]

For Setup analysis, it uses the late value for each startpoint and the early value for each endpoint.
For hold analysis, it uses the early value for each startpoint and the late value for each endpoint.

Fig: Early/Late Source Latency waveforms

The following examples demonstrate how to set different source latency values for rising and falling edges.
To set the expected rise latency to 1.2 and the fall latency to 0.9 for CLK, enter
pt_shell> set_clock_latency -rise 1.2 [get_clocks CLK]
pt_shell> set_clock_latency -fall 0.9 [get_clocks CLK]

To specify an early rise and fall source latency of 0.8 and a late rise and fall source latency of 0.9 for CLK1, enter

pt_shell> set_clock_latency 0.8 -source -early [get_clocks CLK1]

pt_shell> set_clock_latency 0.9 -source -late [get_clocks CLK1]
Clock Uncertainty

Uncertainty = Skew + Jitter + margin