Physical Design world have one critical problem that
if chip have setup violation than we can compromise on the chip performance and we can make chip to work on the lower frequency that it is design
But if chip have Hold violation than one question will arise in mind
'Will it work if we change the frequency ?'
Fig: Setup time and Hold time is meet in the following figure
As shown in figure, in the window of Tsetup and Thold, data must remain stable.
Fig: Hold violation
Figure explain that there is hold violation due to data change in the Thold timing window which result into hold violation.
Now, one solution comes in mind,
'Can we fix the hold violation by reducing the frequency ?'
The Answer is no.
than answer is no, because hold time is independent of frequency.
so, if we find hold violation after the chip design, than it is waste of effort
Fig: Setup time and Hold time is meet in the following figure
As shown in figure, in the window of Tsetup and Thold, data must remain stable.
Fig: Hold violation
Figure explain that there is hold violation due to data change in the Thold timing window which result into hold violation.
Now, one solution comes in mind,
'Can we fix the hold violation by reducing the frequency ?'
The Answer is no.
Now, Lets understand the concept of why hold is free from the frequency?
(means changing the frequency cant fix the hold violation)
(means changing the frequency cant fix the hold violation)
According to hold violation definition, data should remain stable after the active edge of clock for some minimum time
Fig: see the following figure that data is traveling from one ff1 to ff2
data1 = data at ff1
data2 = data at ff2
clock1= launch clock
clock2= capture clock
At the clock1, data1 is being sampled at ff2, and at clock2 data2( data of ff1 that is data1) is already reach to ff2 already
from the figure setup checks equation , that is
Tc2q(ff1) + Tcomb = Tclk - Tsetup
data1 of ff1 at clock1 should reach at ff2 in clock2 before the setup time of ff2.
from the hold checks,that is Tc2q + Tcomb >= T(hold)
data1 should not arrive at ff2 at clock2 before hold time because it override the data2.
which means that data is overridden by next data because data comes to much fast that override the previous data that is captured by previous clock edge, so, functionality of chip is getting failed.
If the delay of combo logic and Tc2q delay is less than the hold time of ff2 than data comes too much fast that which does not give setup violation but result in hold violation, so, due to this condition data that is already capture data at ff2(data2) overrides by the data1 at the clock2 edge.
so, it is only depends on the Tcombo and Tc2q, and Tcombo and Tc2q is not depends upon the clock period or working frequency.
so, Hold is independent of frequency.
Fig: see the following figure that data is traveling from one ff1 to ff2
data1 = data at ff1
data2 = data at ff2
clock1= launch clock
clock2= capture clock
At the clock1, data1 is being sampled at ff2, and at clock2 data2( data of ff1 that is data1) is already reach to ff2 already
from the figure setup checks equation , that is
Tc2q(ff1) + Tcomb = Tclk - Tsetup
data1 of ff1 at clock1 should reach at ff2 in clock2 before the setup time of ff2.
from the hold checks,that is Tc2q + Tcomb >= T(hold)
data1 should not arrive at ff2 at clock2 before hold time because it override the data2.
which means that data is overridden by next data because data comes to much fast that override the previous data that is captured by previous clock edge, so, functionality of chip is getting failed.
If the delay of combo logic and Tc2q delay is less than the hold time of ff2 than data comes too much fast that which does not give setup violation but result in hold violation, so, due to this condition data that is already capture data at ff2(data2) overrides by the data1 at the clock2 edge.
so, it is only depends on the Tcombo and Tc2q, and Tcombo and Tc2q is not depends upon the clock period or working frequency.
so, Hold is independent of frequency.
Thanks for the detailed explanation!!!
ReplyDeleteOne question: Is the following "ff2" supposed to be "ff1"?
ReplyDelete"At the clock1, data1 is being sampled at ff2"
Yes, Me also think so.......it should be : "At the clock1, data1 is being sampled at ff1
DeleteWhat if the path is half cycle.. in that case hold depends on clock period.
ReplyDelete