SDC (Synopsys Design Constraints)

The rules that are written are referred to as constraints and  are essential to meet designs goal in terms of Area, Timing and Power to obtain the best possible implementation of a circuit.

There is a common format, for constraining the design, which is supported by almost all the tools, and this format is called SDC - Synopsis Design Constraints format.

The file is saved with an .sdc extention
SDC syntax is a TCL based format, that is, all commands follow the TCL syntax

SDC contains mainly following constraints that are very essential for design

• Clock definition
• Generated clock
• Input/Output delay
• Min/Max delay
• False path
• Multi cycle path
• Case analysis
• Disable timing arcs

The constraints are the following types according the commands types:

• Basic commands
• Object Access Commands
• Timing Commands
• Environment Commands
• Multi-Voltage Commands

Basic Constraints commands

these commands used to set the attributes from that instance

cmd:    set: used to define variables

for example: set_units [-capacitance cap_unit] [-resistance res_units]

                                     [-time time_unit] [-voltage voltage_unit]

                                     [-current current_unit] [-power power_unit]

Object Access Constraints commands

These commands specify how to access objects in a design instance.

these commands are used to get the location of an object in the design.

the object can be a cell, a block, a port, a pin, or anything else in the design.

for example: 

      all_clocks

      # Returns a collection of all clocks.

      Examples:

      foreach_in_collection clkvar [all_clocks] {

       . . .}

      set_clock_transition 0.150 [all_clocks]

      get_libs [-regexp] [-nocase] patterns

      # Returns a collection of libraries that are currently

      # loaded in the design.

for more commands refer this book : Static Timing Analysis for Nanometer Designs A Practical Approach 

Timing Constraints commands

these commands are related to timing specifications of the design

which contains,

• Clock definition          : create_clock
• Generated clock          : create_generated_clock
• Clock transition          : set_clock_transition
• Clock Uncertainty      : set_clock_uncertainty 
• Clock Latency            : set_clock_latency 
• Propagated clock        : set_propagated_clock
• Disable timing            : set_disable_timing
• False path                   : set_false_path                     
• Input/Output delay     : set_input_delay & set_output_delay
• Min/Max delay           : set_min_delay / set_max_delay
• Multicycle path          : set_multicycle_path

Environmental constraints

these commands are used to setup the environment of the design under analysis

commands are:

set_driving_cell
set_input_transition
set_load
set_max_fanout
set_max_area
set_operating_conditions
set_wire_load_model
set_case_analysis.......etc

Multi-Voltage Commands
these commands apply when multi-voltage islands are present in s design.
commands are:
create_voltage_area
set_level_shifter_strategy
set_level_shifter_threshold

set_max_dynamic_power

set_max_leakage_power

Clock

Design includes the following types of Clock information:

• Multiple clocks:

we can define multiple clocks that have different waveforms and frequencies. 

Clocks can have real sources(ports and pins) or can be virtual( no real source) in the design.

• Gated clock

A gated clock is a clock signal 

under the control of the gating logic

• Generated Clocks

A generated clock is a clock signal generated from another clock signal by a circuit within the design itself, such as a clock divider

• Clock Transition times

 the transition time is the amount of time it takes for the signal to change from one logic state to anoher

• Clock network delay and skew:

we specify the delay of the clock network relative to the source called clock latency  and

the variation of the arrival times of the clock at the destination points in the clock network called clock skew

• Clock Latency: it can be ideal or propagated clocks

it has two types 1). Source Latency 2). Network Latency

Source latency is the delay between the ideal waveform to the source pin or port.

Network latency is the delay between the source pin or port to register clock pin 

If we specify the clock as propagated than PT can automatically compute the clock source latency

If not than user specified value is consider for clock source latency

Fig: External Source Latency

Propagated latency calculation is usually inaccurate for prelayout design because the parasitics are unknown.
For prelayout designs, you can estimate the latency of each clock and directly set that estimation with the
set_clock_latency command and it is known as ideal clocking

To specify an external uncertainty for source latency,
use the -early  and -late options of the set_clock_latency command.

For example, consider a source latency that can vary from 1.5 to 2.5ns as shown in above fig.
to specify this type of source latency, you can use commands such as following:

pt_shell> set_clock_latency 1.5 -source -early [get_clocks CLK]
pt_shell> set_clock_latency 2.5 -source -early [get_clocks CLK]

For Setup analysis, it uses the late value for each startpoint and the early value for each endpoint.
For hold analysis, it uses the early value for each startpoint and the late value for each endpoint.

Fig: Early/Late Source Latency waveforms

The following examples demonstrate how to set different source latency values for rising and falling edges.
To set the expected rise latency to 1.2 and the fall latency to 0.9 for CLK, enter
pt_shell> set_clock_latency -rise 1.2 [get_clocks CLK]
pt_shell> set_clock_latency -fall 0.9 [get_clocks CLK]

To specify an early rise and fall source latency of 0.8 and a late rise and fall source latency of 0.9 for CLK1, enter

pt_shell> set_clock_latency 0.8 -source -early [get_clocks CLK1]

pt_shell> set_clock_latency 0.9 -source -late [get_clocks CLK1]
Clock Uncertainty

Uncertainty = Skew + Jitter + margin

Clock Skew

Clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the clock circuit or source or clock definition point) arrives at different components at different times.
due to

• wire-interconnect length
• temperature variations
• capacitive coupling
• material imperfections and
• differences in input capacitance on the clock inputs 

these factor became more critical for high frequency

Figure: Clock Skew 

there are two types of clock skew

• Negative skew
• positive skew

Positive skew occurs when the transmitting register receives the clock tick earlier than the receiving register.
Negative skew is occurs when the receiving register gets the clock tick earlier than the sending reg

Zero clock skew refers to the arrival of the clock tick simultaneously at transmitting and receiving reg

Skew can be caused two types of violation

• Setup violation 
• Hold violation

When the clock travels slower than the path form the one reg to another allowing data to penetrate two registers in the same clock tick, or maybe destroying the integrity of the latched data. this is called hold violation because the previous data is not held long enough at the destination flop to be properly clocked though.

if the destination flop receives the clock tick earlier than the source flop- the data signal has that much less time to reach the destination flop before the next clock tick, if it is fails to do so,a setup violation occurs, so called new data was not set up and stable before the next clock tick arrived.

Useful Skew
clock skew can also benefit a circuit by decreasing the clock period locally at which the circuit will operate correctly, it means skew add more margin to meet setup. that is called useful skew

for each source register and destination register connected by a path. so, following setup and hold inequalities must be obeyed.

for setup,
               T(clock period)  > = T(reg) + Path dealy(max) + J(jitter) + S(setup time) - Skew
for Hold,
               Skew <= T(reg) + Path delay(min) - J(jitter) - H(hold time)

Positive skews are good for fixing setup violation, but can cause hold violation
Negative skew can help hold violation, but can cause setup violation

Figure :1

Figure 1 show a situation where clock skew can benefit a synchronous circuit
In the zero skew circuit, a long path goes form FF1 to FF2, and short path, from FF2 to FF3,

here, Path FF2 -> FF3 path is close to having a hold violation: if small amount of extra clock delay occurs at FF3, this could destroy the data at D input of FF3 before clock arrives.

Figure 2

Figure 2 shows how the problem can be fixed
for clock skew.
A small amount of extra delay is added before FF2's clock input. with the care the extra delay relaxes the setup constraint for the FF1->FF2
here, for FF1->FF2 operates less than what required for zero skew.
so, some intentional skew helps in proper functioning of circuit,

NOTE: in above example, circuit is closer to malfunctioning- a small amount of positive clock skew for the FF2-> FF3 pair will cause hold violation, whereas the intentional skew(useful skew) circuit helps to meet the setup and hold constraints

Logic Synthesis

Which method would you use to design the logic circuitry for a million gate design?

I think we can use 

• Paper & pencil : but it takes lots of month of time
• Pspice schematic : it takes few month 
• Logic Synthesis: it take very few days

so, Logic synthesis is the method of design which convert the RTL which is in the form of code, can convert to gates level design, which reduced the the ASIC design cycle dramatically.

Logic Synthesis

It is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gate

so, It is the process of Translating, Optimizing and Mapping 

PD interview Questiona - STA

What is crosstalk? What is the effect of crosstalk on timing? How to minimize crosstalk?

Crosstalk is phenomenon in which switching on a signal net effects switching activity of a nearby net due to capacitive coupling between two nets. Due to process-technology scaling, the spacing between adjacent interconnect wires keeps shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. Hence, increase in the crosstalk effect. Crosstalk can severely effect timing in VLSI circuits. 
Cross-talk has two effects. 

1.Crosstalk delay 
2. Crosstalk noise

If if two adjacent wires are switching in opposite direction it will slow down signal hence violating set up time. 
If two net are switching in same direction it will aid timing. This is called crosstalk delay.This is random phenomenon. It depends on switching. 

If one net is switching and other is at constant value. The switching one net can cause induce voltage spike on other net. This is called crosstalk noise.

Methods for minimizing crosstalk:
1. Shielding of victim net by VDD/VSS line.
2. Upsize driver of victim net or downsize driver of aggressor net.
3. Add buffer on victim net.
4. Increase spacing between two nets.

PD interview Questions - Routing

1. What is the basic difference between 9 track and 12 track in standard cells? Who does a track means?

Firstly track can be related to lanes, eg like we say 6 lane road, implies 6 vehicles can run in parallel. So 10 tracks would imply we can route 10 wires in parallel with minimum pitch.

Now, 9/12 track implies 9 routing tracks are available for routing 9 wires in parallel with minimum pitch. For example if for 28nm we are using 9 track standard cell library with minimum metal pitch of 100n. In this case we will have standard cell of height 0.9um (100n*9) where 9 horizontal tracks are available for routing.

2. Why do we use alternate layer horizontal/vertical/horizontal (HVH or VHV) routing?

Some advantages of VHV/HVH:
To make best utilization of placement and routing resources.
To nullify crosstalk from layer beneath and above the routing layer.
More uniform distribution of power.

Why hold is independent of frequency?

Physical Design world have one critical problem that

if chip have setup violation than we can compromise on the chip performance and we can make chip to work on the lower frequency that it is design

But if chip have Hold violation than one question will arise in mind 

             'Will it work if we change the frequency ?'

than answer is no, because hold time is independent of frequency.

so, if we find hold violation after the chip design, than it is waste of effort

Fig: Setup time and Hold time is meet in the following figure

As shown in figure, in the window of Tsetup and Thold, data must remain stable. 








 Fig: Hold violation

Figure explain that there is hold violation due to data change in the Thold timing window which result into hold violation.





Now, one solution comes in mind,
'Can we fix the hold violation by reducing the frequency ?' 

The Answer is no.

Now, Lets understand the concept of why hold is free from the frequency?
(means changing the frequency cant fix the hold violation)

According to hold violation definition, data should remain stable after the active edge of clock for some minimum time

Fig: see the following figure that data is traveling from one ff1 to ff2

data1 = data at ff1
data2 = data at ff2
clock1= launch clock
clock2= capture clock


At the clock1, data1 is being sampled at ff2, and at clock2 data2( data of ff1 that is data1) is already reach to ff2 already

from the figure setup checks equation , that is
Tc2q(ff1) + Tcomb = Tclk - Tsetup
data1 of ff1 at clock1 should reach at ff2 in clock2 before the setup time of ff2.

from the hold checks,that is Tc2q + Tcomb >= T(hold)
data1 should not arrive at ff2 at clock2 before hold time because it override the data2.

which means that data is overridden by next data because data comes to much fast that override the previous data that is captured by previous clock edge, so, functionality of chip is getting failed.

If  the delay of combo logic and Tc2q delay is less than the hold time of ff2 than data comes too much fast that which does not give setup violation but result in hold violation, so, due to this condition data that is already capture data at ff2(data2) overrides by the data1 at the clock2 edge.
 so, it is only depends on the Tcombo and Tc2q, and Tcombo and Tc2q is not depends upon the clock period or working frequency.

so, Hold is independent of frequency.