What is the difference between a latch and a flip-flop?

Both latches and flip-flops are circuit elements whose output depends not only on the
present inputs, but also on previous inputs and outputs.

• They both are hence referred as "sequential" elements.
• In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements, while slightly more advanced  non-transparent (or clocked) devices are described as flip-flops. Informally, as this distinction is quite new, the two words are sometimes used interchangeably. [wiki] 
• In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states and thereby is capable of serving as one bit of memory. 
• Today, the term flip-flop has come to generally denote non-transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.[wiki]
• A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal. 
• Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock is logic 1, the output can change if the input also changes.
• Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the clock. 
• A positive level latch is transparent to the positive level(enable), and it latches the final input before it is changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)
• A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for negative edge flop) only. 
• Latches are faster, flip flops are slower.
• Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
• Latches take less gates (less power) to implement than flip-flops.
• D-FF is built from two latches. They are in master slave configuration.
• Latch may be clocked or clock less. But flip flop is always clocked.
• For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup and hold time are very important.

Cells Types in PD

In Physical Design flow, there are various kinds of cells used for several functionality. Each individual cells has there own functionality with which they are implemented in design. Here are some of the list of cells and their basic importance.

Spare Cells

When the design is tape-out and afterwards there is a requirement to fix some bug then it is not possible to fix if we haven’t provided spare cells. These are kind of floating cells which are thrown in design so that after tape-out if some bugs are needed to fix, we can take use of it.There would be inclusion of approximately 5% of spare cells in the whole design, not more than that.

Decap Cells 

They are temporary capacitors which are added in the design between power and ground rails to counter the functional failure due to dynamic IR drop. Dynamic IR Drop happens at the active edge of the clock at which a high current is drawn from the power grid for a small duration. If power source is far from a flop the chances are there that flop can go into metastable state. To overcome decaps are added, when current requirement is high this decaps discharge and provide boost to the power grid.

Detailed Discussion:http://www.cadence.com/Community/forums/p/11345/17149.aspx

Tie Cells

Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. These cells are part of standard-cell library. The cells which require Vdd (Typically constant signals tied to 1) connect to Tie high cells The cells which require Vss/Gnd (Typically constant signals tied to 0) connect to Tie Low cells.

For more details:

http://www.cadence.com/Community/forums/p/12129/16444.aspx

Well taps (Tap Cells)

They are traditionally used so that Vdd or GND are connected to substrate or n-well respectively. This is to help tie Vdd and GND which results in lesser drift and prevention from latchup.End cap Cells: The library cells do not have cell connectivity as they are only connected to power and ground rails, thus to ensure that gaps do not occur between well and implant layer and to prevent the DRC violations by satisfying well tie-off requirements for core rows we use end-cap cells.

Filler cells

Filler cells are used to establish the continuity of the N- well and the implant layers on the standard cell rows, some of the small cells also don’t have the bulk connection (substrate connection) because of their small size (thin cells). In those cases, the abutment of cells through inserting filler cells can connect those substrates of small cells to the power/ground nets. i.e. those thin cells can use the bulk connection of the other cells (this is one of the reason why you get stand alone LVS check failed on some cells).

PD Interview Questions - How does DFT logic affect PD ?

1. How does mbist logic affect placement ? Will knowing the algorithms used to assign controllers help in floorplan ? How does scan chain affect PD ?

MBIST (Memory built-in self-test) logic is inserted to test the memories. It contains MBIST processor & wrapper around the memories. MBIST processor controls the wrapper & generates various control signals during the memory testing. A single block may have multiple processors depending on the number of memories, memory size, power and memory placement. Memory placed nearby are grouped together & controlled by a single processor. 
Memory placement information needs to be given to the DFT team in form of DEF & floorplan snapshot (optional). 
If memories are not grouped properly according to their physical location i.e memories under same processors are sitting far apart. This will lead to MBIST logic spreading. 
This may have impact on MBIST timing due to long paths or increase in congestion due to lots of criss-cross.

2. what you mean by Scan Chain Reordering?

click on link for more information

http://vlsibasic.blogspot.in/2014/09/scan-chain-reordering.html

Scan Chain Reordering

It is the process of reconnecting the scan chains in a design to optimize for routing by reordering the scan connection which improve timing and congestion.
Since logic synthesis arbitrarily connects the scan chain, we need to perform scan reorder after placement so that the scan chain routing will be optimal
Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys) and can reorder to optimize it & it maintains the number of flops in a chain.

Physical Netlist is reordered based on placement
Reordered scan chain requires much less routing resources in the example design.

Congestion Effect:

During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion.

Timing Effect:

This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock domains.
Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be redone by reading the new netlist.

PD Intervie Questions - Floorplanning

PowerPlanning