DRC

DRC is nothing but Design Rule Check. After routing, In Physical Verification steps we do DRC clean up. It means it should follows all foundry rules/run sets to create appropriate mask. We already know that chip manufacturing process is not ideal. DRC ensure that design will still work properly even there may be lot of misalignment and various side effects of fabrication process. There are multiple reason behind this. We will discuss all the major reason behind this. 

Aim of physical Design cycle is to deliver GDS II to foundry such a way that it should be Timing & Physically clean. Here physically clean it means your GDS II should meet DRC/LVS/ERC/Antenna. There are EDA tools are available in market which reads your GDS II and do simulation with run sets and give your DRC errors which needs to clean. 

·  All foundries have their own design rules for masking. They have consistent process to convert GDS II in to real layout/final product. As per technology and process information they define some set of rules which has to follow by Physical Design Engineer while delivered GDS II.

·   Design Rules defines shapes/size/spacing and many other complex rules of each metal layers. It starts from your substrate to Newell to top metal layers.

·   All rules are define in one rule deck file, Its nothing but your drc runset file. For routing purpose, minimum set of rules will be define your technology file.  Which extension is .tf.

·  Each foundry have its own manufacturing design rules. DRC rules becoming complex as we are going sub-micron technology.

· DRC doesn’t ensure that your device will work properly, It ensure it will get manufactured properly.

· Once Design is DRC clean, then only correct parasitic extraction we can get.

DRC Flow

 DRC clean up comes in Physical Verification steps (After routing). If you are working on below 90nm , Metal Fill is required. So once you finish metal fill you will have corrected DRCs errors. Below DRC flow input/output and some basic examples are given. 

INPUT

·         GDS II of your block/section/chip in format of .stm or .oasis

·         DRC runset file. Extenuation of runset file depend on which EDA tools you are working on. Normally it’s in .ev or .rs 

OUTPUT

•  Marker based error file.
• If you are using Synopsys Tools ( IC Validator ) It generates .vue file.
• This files can be loaded and we can go to one by one markers and clean drcs.

Basic Examples.

1.       DRC_M2: Minimum distance BW M2 should be  0.070.

Error Description: Here spacing BW metal2 is 0.046 which should be 0.070.     

Solution: Stretch metal/fill by keeping spacing 0.070 BW them.

2. DRC_M4 : Width1 to width2 spacing should be 0.040

Error Description: Here two different width of metal4 width to width spacing is not as per rule

EDA TOOLS

·         Synopsys :  IC Validator or Hercules

·         Mentor Graphics : Caliber

Electrical Rules Checking (ERC)

ERC Rules check for things such as:

• Floating gates.
• Wrong transistor connections (Source and Drain connected together for instance).
• Floating interconnect, Metal, Poly
• Shorted Drain & Source of a MOS 
• No substrate- or well contact ('figure having no stamped connection') 
• Different contacts of substrate / well are connected to different nets
• Distance of MOS to next substrate / well contact too large (Latchup rule) 

Often reported errors are deliberate, for example a gate may have its source and drain connections deliberate connected together to produce a capacitor.

Layout vs Schematic Verification (LVS)

• Verify that physical implementation is consistent with the above gate and RTL level design representations

• Errors may have occurred due to 

–Errors in physical design tools

–Manual changes in layout

• Verification is primarily graphical or ``topological’’:   gate identification from transistor networks, subgraph isomorphism

Goals: Functionality

Analysis Inputs:

- Foundary or library vendor : Library & Spice Netlist

- Design Data: Mask Data, Logic Netlist

Typical checks perfomed

- connectivity recognition

- device recognition

What LVS does
3 Steps:
1. Extract schematic netlist
2. Extract the layout netlist 
3. Compare the two netlists

In most cases the layout will not pass LVS the first time requiring the layout engineer to examine the LVS software's reports and make changes to the layout. Typical errors encountered during LVS include:

1. Shorts: Two or more wires that should not be connected have been and must be separated.
2. Opens: Wires or components that should be connected are left dangling or only partially connected. These must be connected properly to fix this.
3. Component Mismatches: Components of an incorrect type have been used (e.g. a low Vt MOS device instead of a standard Vt MOS device)
4. Missing Components: An expected component has been left out of the layout.
5. Parameter Mismatch