Die Size Estimation

Technology Inputs:
Gate Density per sq. mm = D
Number of Horizontal Layers = H
Number of Vertical Layers = V

Design Inputs:
Gate count (excluding memories, macros & subchips) = G
IO area, in sq. mm = I
Memory + Macros + Subchips area, in sq.mm = M
Target Utilization, in percentage = U %
Additional gate count for CTS, timing closure etc, in percentage = T %
Additional gate count for ECOs, in percentage = E %

Die area calculation:

Die Area in sq.mm = {[(Gate count + Additional gate count for CTS & ECO) / Gate density] + IO                                           area + Mem, Macro area} / Target utilization

Die Area = {[(G + T + E) / D] + I + M} / U


Aspect ratio, width, height calculation:

Aspect Ratio
                                 AR = width / height
                                       = Number of horizontal resources / Number of vertical resources
                                 AR = H / V

Height
                AR = W / H
                 W = H * AR ----- (1)
           
             Area = W * H
                     = H * H * AR (Expressing W in terms of H from (1)
                H2 = Area / AR
                 H = SQRT (Die Area / AR)

Width

                W = H * AR


Aspect ratio is defined as the ratio of height to width