For technology nodes below 40nm, there are few important rules that must be considered while creating the floorplan.
In fabrication of semiconductors, the minimum line width of the circuit element is called critical dimension (CD). The smaller the circuit element is, the less variation of the CD is allowed. So fabrication of these smaller elements is a big challenge due to critical dimension uniformity (CDU) which impacts the device performance and its characteristics. CDU is a major contributor to yield drop out in deep sub micron technologies Thus, many techniques for improving the critical dimension uniformity are developed,
TCD structures are placed to monitor these various processes variation on the die.
The TCD structure is required to be placed at regular intervals throughout the chip.It could be a significant size, which may need to be allocated on the die early on.
This may impact a floorplan of a block at a later stage if this fact is not considered early on, such as in a block packed with memories.
These are inserted after power planning also we can stack BEOL TCDs over FEOL TCDs to save placement area but BEOL TCDs with metal layer M cannot place over layer M routing.
If a FEOL TCD is on layer M routing, then a BEOL TCD with metal layer M cannot stack with this FEOL TCD.
TCD width and height are not even multiples of unit tile width and height. They are placed
similar to regular macros.
This is one of few of the mandatory components that must be considered in the early stages of full-chip floorplanning, and must be considered for block-level floorplanning.
why generated clock is actually required, sometimes i have seen that there is devide by 1 generated clock is also thre then why it is required, why not we are using master clock only for devide by 1?
ReplyDeleteThanks Sagar, I searched through all the fab's docs trying to remember what the "T" stood for in TCD with no luck. I should have tried Google first, but I usually don't have much luck with these types of acronyms. Would be nice to have a comprehensive VLSI acronym dictionary, but it's hard to tip toe the NDA line.
ReplyDelete