Fig: following is the flow of how design is processing in the one level to other level
Figure shows that how one idea that is written in some code, that is converting into the physible chip.
Where,
System level
- It is the abstract algorithmic description of high level behavior which is written in higher level language like C and it does not contain any implementation details for timing or data
RTL level
- It is accurate model very close to the hardware implementation which is describe in bit level
- it contains sequential constructs like if-than-else, while loops...... to support the modeling of complex control flow. for example:
module mark1;
reg [31:0] m[0:8192];
reg [12:0] pc;
reg [31:0] acc;
reg[15:0] ir;
always
begin
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...
end
endmodule
Gate level
- it is describes models function in Boolean logic using registers and gates
- various delay models for gates and wires is defined
Transistor level
- it is describe in the form of CMOS
- depending on the application function modeled as resistive switches or full differential equations for circuit simulations
Layout level
- transistor and wires are laid out as polygons in different technology layers such as diffusion, ploy-silicon, metals etc.
Figure shows that how one idea that is written in some code, that is converting into the physible chip.
Where,
System level
- It is the abstract algorithmic description of high level behavior which is written in higher level language like C and it does not contain any implementation details for timing or data
RTL level
- It is accurate model very close to the hardware implementation which is describe in bit level
- it contains sequential constructs like if-than-else, while loops...... to support the modeling of complex control flow. for example:
module mark1;
reg [31:0] m[0:8192];
reg [12:0] pc;
reg [31:0] acc;
reg[15:0] ir;
always
begin
ir = m[pc];
if(ir[15:13] == 3b’000)
pc = m[ir[12:0]];
else if (ir[15:13] == 3’b010)
acc = -m[ir[12:0]];
...
end
endmodule
Gate level
- it is describes models function in Boolean logic using registers and gates
- various delay models for gates and wires is defined
Transistor level
- it is describe in the form of CMOS
- depending on the application function modeled as resistive switches or full differential equations for circuit simulations
Layout level
- transistor and wires are laid out as polygons in different technology layers such as diffusion, ploy-silicon, metals etc.
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