- Clock Tree Synthesis is a process which makes sure that the clock gets distributed evenly to all sequential elements in a design.
- The goal of CTS is to minimize the skew and latency.
- The placement data will be given as input for CTS, along with the clock tree constraints.
- The clock tree constraints will be Latency, Skew, Maximum transition, Maximum capacitance, Maximum fan-out, list of buffers and inverters etc.
- The clock tree synthesis contains clock tree building and clock tree balancing.
- Clock tree can be build by clock tree inverters so as to maintain the exact transition (duty cycle) and clock tree balancing is done by clock tree buffers (CTB) to meet the skew and latency requirements.
- Less clock tree inverters and buffers should be used to meet the area and power constraints.
- There can be several structure for clock tree:
- Multi level clock tree
- Fish bone
- Once the CTS is done than we have to again check the timing.
- The outputs of clock tree synthesis are Design Exchange Format (DEF), Standard Parasitic Exchange Format (SPEF), and Netlist etc.
- The normal inverters and buffers are not used for building and balancing because, the clock buffers provides a better slew and better drive capability when compared to normal buffers and clock inverters provides a better balance with rise and fall times and hence maintaining the 50% duty cycle.
- Effects of CTS: Many clock buffers are added, congestion may increase, crosstalk noise, crosstalk delay etc.
- Clock tree optimizations: It is achieved by buffer sizing, gate sizing, HFN synthesis, Buffer relocation.
Set Up Fixing:
- Upsizing the cells (increase the drive strength) in data path.
- Pull the launch clock
- Push the capture clock
- We can reduce the buffers from datapath .
- We can replace buffers with two inverters placing farther apart so that delay can adjust.
- We can also reduce some larger than normal capacitance on a cell output pin.
- We can upsize the cells to decrease the delay through the cell.
- LVT cells
It is well understood hold time will be large if data path has more delay. So we have to add more delays in data path.
- Downsizing the cells (decrease the drive strength) in data path.
- Pulling the capture clock.
- Pushed the launch clock.
- By adding buffers/Inverter pairs/delay cells to the data path.
- Decreasing the size of certain cells in the data path, It is better to reduce the cells n capture path closer to the capture flip flop because there is less chance of affecting other paths and causing new errors.
- By increasing the wire load model, we can also fix the hold violation.
In some cases, signal takes too long transiting from one logic level to another, than a transition violation is caused. The Trans violation can be because of node resistance and capacitance.
- By upsizing the driver cell.
- Decreasing the net length by moving cells nearer (or) reducing long routed net.
- By adding Buffers.
- By increase the width of the route at the violation instance pin. This will decrease the resistance of the route and fix the transition violation.
The capacitance on a node is a combination of the fan-out of the output pin and capacitance of the net. This check ensures that the device does not drive more capacitance than the device is characterized for.
- The violation can be removed by increasing the drive strength of the cell.
By buffering the some of the fan-out paths to reduce the capacitance seen by the output pin.